A 16Gb 18Gb/S/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking-Reference-Cited by-同舟云学术

A 16Gb 18Gb/S/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking

Published:2018-02 Issue: Volume: Page:
ISSN:
Container-title:2018 IEEE International Solid - State Circuits Conference - (ISSCC)
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Author:

Kim Young-Ju,Kwon Hye-Jung,Doo Su-Yeon,Eom Yoon-Joo,Kim Young-Sik,Ahn Min-Su,Kim Yong-Hun,Jung Sang-Hoon,Do Sung-Geun,Lee Chang-Yong,Kim Jae-Sung,Kang Dong-Seok,Park Kyung-Bae,Shin Jung-Bum,Lee Jong-Ho,Oh Seung-Hoon,Lee Sang-Yong,Yu Ji-Hak,Kwon Ji-Suk,Yu Ki-Hun,Jeon Chul-Hee,Kim Sang-Sun,Won Min-Woo,Cho Gun-hee,Park Hyun-Soo,Kim Hyung-Kyu,Lee Jeong-Woo,Cho Seung-Hyun,Park Keon-Woo,Park Jae-Koo,Lee Yong-Jae,Kim YongJun,Seo Young-Hun,Cho Beob-Rae,Shin Chang-Ho,Lee Chan-Yong,Lee YoungSeok,Song Yoon-Gue,Bang Sam-Young,Park YounSik,Choi Seouk-Kyu,Kim Byeong-Cheol,Han Gong-Heum,Bae Seung-Jun,Kwon Hyuk-Jun,Choi Jung-Hwan,Sohn Young-Soo,Park Kwang-Il,Jang Seong-Jin

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/8304413/8310156/08310255.pdf?arnumber=8310255

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