A 60nm 6Gb/s/pin GDDR5 Graphics DRAM with Multifaceted Clocking and ISI/SSN-Reduction Techniques-Reference-Cited by-同舟云学术

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A 60nm 6Gb/s/pin GDDR5 Graphics DRAM with Multifaceted Clocking and ISI/SSN-Reduction Techniques

Published:2008-02 Issue: Volume: Page:
ISSN:
Container-title:2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers
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Author:

Bae Seung-Jun,Sohn Young-Soo,Park Kwang-Il,Kim Kyoung-Ho,Chung Dae-Hyun,Kim Jin-Gook,Kim Si-Hong,Park Min-Sang,Lee Jae-Hyung,Bang Sam-Young,Lee Ho-Kyung,Park In-Soo,Kim Jae-Sung,Kim Dae-Hyun,Kim Hye-Ran,Shin Yong-Jae,Park Cheol-Goo,Moon Gil-Shin,Yeom Ki-Woong,Kim Kang-Young,Lee Jae-Young,Yang Hyang-Ja,Jang Seong-Jin,Choi Joo Sun,Jun Young-Hyun,Kim Kinam

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/4497158/4523032/04523165.pdf?arnumber=4523165

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2. Research on Acceleration Technologies and Recent Advances of Data Center GPUs;2023 8th International Conference on Intelligent Computing and Signal Processing (ICSP);2023-04-21

3. A Summer-Embedded Sense Amplifier for High-Speed Decision Feedback Equalizer;IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences;2018-11-01

4. Timing Circuit Design in High Performance DRAM;CMOS Processors and Memories;2010

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