A 3$\,\times\,$5-Gb/s Multilane Low-Power 0.18-$\mu{\hbox {m}}$ CMOS Pseudorandom Bit Sequence Generator-Reference-Cited by-同舟云学术

登录注册会员服务联系我们

A 3$\,\times\,$5-Gb/s Multilane Low-Power 0.18-$\mu{\hbox {m}}$ CMOS Pseudorandom Bit Sequence Generator

Published:2008-05 Issue:5 Volume:55 Page:432-436
ISSN:1549-7747
Container-title:IEEE Transactions on Circuits and Systems II: Express Briefs
language:
Short-container-title:IEEE Trans. Circuits Syst. II

Author:

Kin-Joe Sham ,Bommalingaiahnapallya S.,Ahmadi M.R.,Harjani R.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx5/8920/4522633/04420096.pdf?arnumber=4420096

Cited by 18 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. 16.8 Gbps Fully-Differential Pseudorandom Bit Sequence Generator Exploiting Asynchronous XOR Gate with an FOM of 1.1 pJ/bit on 65-nm CMOS;2024 13th International Conference on Modern Circuits and Systems Technologies (MOCAST);2024-06-26

2. A 2⁷-1, 20-Gb/s, 0.1-pJ/b Pseudo Random Bit Sequence Generator Using Incomplete Settling in 1.2V, 65 nm CMOS;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

3. A 15-Gb/s, 0.036 pJ/bit, Half-Rate, Low Power PRBS Generator in 1.2 V, 65 nm CMOS;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

4. A PRBS Generator Using Merged XOR-D Flip-Flop as Building Blocks;Circuits, Systems, and Signal Processing;2023-06-19

5. An active inductor employed CML latch for high speed integrated circuits;Analog Integrated Circuits and Signal Processing;2022-08-03

同舟云学术

1.学者识别学者识别

2.学术分析学术分析

3.人才评估人才评估

"同舟云学术"是以全球学者为主线，采集、加工和组织学术论文而形成的新型学术文献查询和分析系统，可以对全球学者进行文献检索和人才价值评估。用户可以通过关注某些学科领域的顶尖人物而持续追踪该领域的学科进展和研究前沿。经过近期的数据扩容，当前同舟云学术共收录了国内外主流学术期刊6万余种，收集的期刊论文及会议论文总量共计约1.5亿篇，并以每天添加12000余篇中外论文的速度递增。我们也可以为用户提供个性化、定制化的学者数据。欢迎来电咨询！咨询电话：010-8811{复制后删除}0370

www.globalauthorid.com

TOP