An Asynchronous Bundled-Data Template With Current Sensing Completion Detection Technique-Reference-Cited by-同舟云学术

An Asynchronous Bundled-Data Template With Current Sensing Completion Detection Technique

Published:2022-09 Issue:9 Volume:69 Page:3904-3908
ISSN:1549-7747
Container-title:IEEE Transactions on Circuits and Systems II: Express Briefs
language:
Short-container-title:IEEE Trans. Circuits Syst. II

Author:

Huang Yuhao¹^ORCID,Xiao Shanlin²^ORCID,Li Zhiyu¹^ORCID,Yu Zhiyi²^ORCID

Affiliation:

1. School of Electronics and Information Technology, Sun Yat-sen University, Guangzhou, China

2. School of Microelectronics Science and Technology, Guangdong Provincial Key Laboratory, Optoelectronic Information Processing Chips and Systems, Sun Yat-sen University, Zhuhai, China

Funder

National Key Research and Development Program of China

National Natural Science Foundation of China

Key-Area Research and Development Program of Guangdong Province

Zhuhai Industry-Academic Collaboration Program

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/8920/9869776/09762334.pdf?arnumber=9762334

Reference20 articles.

1. Current sensing methodology for completion detection in self-timed systems

2. Self-timed logic using current-sensing completion detection (CSCD)

3. Minimum-Energy Sub-threshold Self-Timed Circuits: Design Methodology and a Case Study

4. Current sensing completion detection in dual-rail asynchronous systems

5. Click Elements: An Implementation Style for Data-Driven Compilation

Cited by 4 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. LAC: A Novel Lightweight Asynchronous Controller With Optimized Phase Shift;IEEE Transactions on Circuits and Systems II: Express Briefs;2024-08

2. Design of High-Performance while Energy-Efficient Microprocessor with Novel Asynchronous Techniques: (PhD Forum Paper);2024 IEEE 35th International Conference on Application-specific Systems, Architectures and Processors (ASAP);2024-07-24

3. Better-Than-Worst-Case: A Frequency Adaptation Asynchronous RISC-V Core With Vector Extension;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024-06

4. Core Interface Optimization for Multi-core Neuromorphic Processors;2023 28th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC);2023-07-16