Better-Than-Worst-Case: A Frequency Adaptation Asynchronous RISC-V Core With Vector Extension-Reference-Cited by-同舟云学术

Better-Than-Worst-Case: A Frequency Adaptation Asynchronous RISC-V Core With Vector Extension

Published:2024-06 Issue:6 Volume:32 Page:1045-1057
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Zhou Lingfeng¹^ORCID,Xiao Shanlin²^ORCID,Wang Huiyao¹^ORCID,Wang Jinghai¹,Xu Zeyang¹^ORCID,Wang Bohan¹^ORCID,Yu Zhiyi²^ORCID

Affiliation:

1. School of Microelectronics Science and Technology, Sun Yat-sen University, Zhuhai, China

2. School of Microelectronics Science and Technology, Guangdong Provincial Key Laboratory of Optoelectronic Information Processing Chips and Systems, Sun Yat-sen University, Zhuhai, China

Funder

National Natural Science Foundation of China

Key-Area Research and Development Program of Guangdong Province

Huawei Technologies Company Ltd

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Link

http://xplorestaging.ieee.org/ielx7/92/10536717/10475190.pdf?arnumber=10475190

Reference48 articles.

1. A Data-Driven Asynchronous Neural Network Accelerator

2. Principles of Asynchronous Circuit Design

3. A Designer's Guide to Asynchronous VLSI

4. Asynchronous Design—Part 1: Overview and Recent Advances

5. Asynchronous Design—Part 2: Systems and Methodologies

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