High Order Mismatch Shaping for Low Oversampling Rates
Author:
Funder
Enterprise Ireland
Science Foundation Ireland
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/8920/8941151/08664116.pdf?arnumber=8664116
Cited by 7 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. A Spur-free Dynamic Element Matching Scheme for Bandpass DACs;2023 21st IEEE Interregional NEWCAS Conference (NEWCAS);2023-06-26
2. An NS-SAR ADC with Full-bit High-order Mismatch Shaped CDAC;2023 IEEE International Symposium on Circuits and Systems (ISCAS);2023-05-21
3. A 16-Bit 4.0-GS/s Calibration-Free 65 nm DAC Achieving >70 dBc SFDR and < −80 dBc IM3 Up to 1 GHz With Enhanced Constant-Switching-Activity Data-Weighted-Averaging;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-05
4. A Small-Area, Low-Power Delta-Sigma DAC Applied to a Power-Specific Chip;Journal of Sensors;2021-05-23
5. Comparison of High-Order Programmable Mismatch Shaping Bandpass DEM Implementations Applicable to Nyquist-Rate D/A Converters;IEEE Open Journal of Circuits and Systems;2021
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