A Small-Area, Low-Power Delta-Sigma DAC Applied to a Power-Specific Chip

Abstract

This paper introduces a small-area, low-power delta-sigma DAC that can support power line carrier communication. In order to achieve the oversampling ratio of 128, a three-stage cascaded half-band filter is utilized. An optimized sturdy MASH $\Delta \Sigma$ modulator was used to avoid instability caused by high-order shaping and reduce the area at the same time. The postanalog reconstruction includes a switched-capacitor DAC (SC DAC) and a 4-tap FIR/IIR hybrid filter, which not only meets the requirements of low power but also promotes the out-of-band SNR. The final chip is fabricated in a 55 nm CMOS process, occupies 0.08 mm2, and consumes 1.5 mW of analog power at 2.5 V supply. The simulation results show that the dynamic range is 85.7 dB, while the out-of-band SNR is 40.5 dB.