A Modified Proportional–Integral Loop Filter to Suppress DCO Noise in Digital PLL

Author:

Namgoong Won

Funder

National Science Foundation

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Cited by 7 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Design and implementation of a low-area reconfigurable and synthesizable digital loop filter for ADPLL;2023 Fourteenth International Conference on Ubiquitous and Future Networks (ICUFN);2023-07-04

2. Design of DTMOS based third-order G$$_m$$-C filter for fast locking PLL;Analog Integrated Circuits and Signal Processing;2022-08-12

3. A low jitter and fast locking all digital phase locked loop with flash based time to digital converter and gain calibrated voltage controlled oscillator;International Journal of Circuit Theory and Applications;2022-05-03

4. A 1 μs Locking Time Dual Loop ADPLL with Foreground Calibration-Based 6 ps Resolution Flash TDC in 180 nm CMOS;Circuits, Systems, and Signal Processing;2021-11-10

5. Three-Phase Phase-Locked Loop Algorithms Based on Sliding Modes;IEEE Transactions on Power Electronics;2021-09

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