Design and implementation of a low-area reconfigurable and synthesizable digital loop filter for ADPLL
Author:
Affiliation:
1. Sungkyunkwan University,Dept. of Electrical & Computer Engineering,Suwon,South Korea
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10199107/10199171/10199652.pdf?arnumber=10199652
Reference5 articles.
1. An Optimum Loop Gain Tracking All-Digital PLL Using Autocorrelation of Bang–Bang Phase-Frequency Detection
2. Design of a wideband digitally controlled oscillator
3. A Modified Proportional–Integral Loop Filter to Suppress DCO Noise in Digital PLL
4. A design methodology for a low power bang-bang all digital PLL based on digital loop filter programmable coefficients
5. A novel digital loop filter with frequency error prediction for fast-locking bang-bang ADPLL
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