A 1 μs Locking Time Dual Loop ADPLL with Foreground Calibration-Based 6 ps Resolution Flash TDC in 180 nm CMOS
Author:
Publisher
Springer Science and Business Media LLC
Subject
Applied Mathematics,Signal Processing
Link
https://link.springer.com/content/pdf/10.1007/s00034-021-01861-z.pdf
Reference30 articles.
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2. N. Pourmousavian, F.-W. Kuo, T. Siriburanon, M. Babaie, R.B. Staszewski, A 0.5-V 1.6-mW 2.4-GHz fractional-N all digital PLL for bluetooth LE with PVT-insensitive TDC using switched-capacitor doubler in 28-nm CMOS. IEEE J Solid-State Circuits (JSSC) 53(9), 2572–2583 (2018). https://doi.org/10.1109/JSSC.2018.2843337
3. R.B. Staszewski, K. Waheed, F. Dulger, O. Eliezer, Spur-free multirate all-digital PLL for mobile phones in 65nm CMOS. IEEE J. Solid-State Circuits (JSSC) 46(12), 2904–2919 (2011). https://doi.org/10.1109/JSSC.2011.2162769
4. Z. Song, B. Chi, Two 180 nm CMOS wireless trans-receivers for IoT applications. in URSI Asia-Pacific Radio Science Conf. (URSI AP-RASC), Seoul, South Korea (2016), pp. 1000–1002. https://doi.org/10.1109/URSIAP-RASC.2016.7601311
5. Roland E. Best, Phase-Locked Loops (McGraw Hill Professional engineering, 2003).
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