Process and temperature robust time‐difference amplifier with analog calibration
Author:
Affiliation:
1. Instituto Nacional de Astrofísica Óptica y Electrónica Luis Enrique Erro 1 Puebla Mexico
Publisher
Institution of Engineering and Technology (IET)
Subject
General Engineering,Energy Engineering and Power Technology,Software
Link
https://onlinelibrary.wiley.com/doi/pdf/10.1049/tje2.12135
Reference8 articles.
1. A 16-bit 2.0-ps Resolution Two-Step TDC in 0.18- $\mu$ m CMOS Utilizing Pulse-Shrinking Fine Stage With Built-In Coarse Gain Calibration
2. A 529-μW Fractional-N All-Digital PLL Using TDC Gain Auto-Calibration and an Inverse-Class-F DCO in 65-nm CMOS
3. An 802.11a/b/g/n Digital Fractional- $N$ PLL With Automatic TDC Linearity Calibration for Spur Cancellation
4. A 1 μs Locking Time Dual Loop ADPLL with Foreground Calibration-Based 6 ps Resolution Flash TDC in 180 nm CMOS
5. A REVIEW OF CMOS TIME-TO-DIGITAL CONVERTER
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