Temperature Compensation in CMOS Peaking Current References
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/8920/8447179/08290961.pdf?arnumber=8290961
Cited by 14 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. A 23.9-μW 13.6-Bit Period Modulation-Based Capacitance-to-Digital Converter With Dynamic Current Mirror Front-End;IEEE Solid-State Circuits Letters;2024
2. A nA-Range Area-Efficient Sub-100-ppm/$^\circ$C Peaking Current Reference Using Forward Body Biasing in 0.11-$\mu$m Bulk and 22-nm FD-SOI;IEEE Journal of Solid-State Circuits;2024
3. A High PSRR CMOS Voltage and Current Reference in One Circuit Without Amplifier for Low Power Applications;2023 International Conference on Microelectronics (ICM);2023-12-17
4. A 23.9 µW 13.6-bit Period Modulation-Based Capacitance-to-Digital Converter with Dynamic Current Mirror Front-end Achieving Capacitor Range of 1 to 68 pF;2023 IEEE Asian Solid-State Circuits Conference (A-SSCC);2023-11-05
5. A 250pA, Gate-Leakage Based Trimming Free Current Reference, from −55°C to 150°C for Lower Power IoT Applications;2023 IEEE 66th International Midwest Symposium on Circuits and Systems (MWSCAS);2023-08-06
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