Energy-Efficient Data-Aware SRAM Design Utilizing Column-Based Data Encoding
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/8920/9204872/08930626.pdf?arnumber=8930626
Cited by 10 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
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3. A 210-MHz 4.23 fJ Energy/Bit 1-kb Asymmetrical Schmitt-Trigger-Based SRAM Using 40-nm CMOS Process;IEEE Transactions on Circuits and Systems II: Express Briefs;2023-10
4. A 1.0 fJ energy/bit single‐ended 1 kb 6T SRAM implemented using 40 nm CMOS process;IET Circuits, Devices & Systems;2023-01-10
5. A Read-Decoupled Error-Tolerant 10T SRAM Cell in 32nm CMOS Technology;Jordan Journal of Electrical Engineering;2023
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