Funder
VLSI Design and Education Center
University of Tokyo in collaboration with Synopsys, Inc.
Cadence Design Systems, Inc.
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Cited by
11 articles.
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1. Architectural analysis of 1-D to 2-D array conversion of priority encoder;International Journal of System Assurance Engineering and Management;2023-07-04
2. Hardware Efficient Weight-Binarized Spiking Neural Networks;2023 Design, Automation & Test in Europe Conference & Exhibition (DATE);2023-04
3. Architectural Improvement and Performance Evaluation of 1D-to-2D Array Conversion Priority Encoder;2022 International Conference on Smart Generation Computing, Communication and Networking (SMART GENCON);2022-12-23
4. 64-bit Multi-match Priority Encoder (MPE64) for High Performance VLSI Architectures;2022 2nd International Conference on Power Electronics & IoT Applications in Renewable Energy and its Control (PARC);2022-01-21
5. A Novel low power 2-D to 3-D Array Priority Encoder using Split-Logic Technique for Data Path Applications;WSEAS TRANSACTIONS ON SYSTEMS AND CONTROL;2022-01-07