64-bit Multi-match Priority Encoder (MPE64) for High Performance VLSI Architectures

Author:

Pradeep A1,Radha S1,Sujay Nestham1,Ram Panchagnula Venkata Janaki1,Ganesh G Venkata1,Nagabushanam P2

Affiliation:

1. Karunya Institute of Technology and Sciences,Department of ECE,CBE,IN

2. Karunya Institute of Technology and Sciences,Department of EEE,CBE,IN

Publisher

IEEE

Reference16 articles.

1. A VLSI High-Performance Priority Encoder Using Standard CMOS Library

2. A BCD priority encoder designed by reversible logic;wang;In 2012 International Conference on Wavelet Active Media Technology and Information Processing (ICWAMTIP),2012

3. A power-optimized 64-bit priority encoder utilizing parallel priority look-ahead;kun;In 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat No 04CH37512),2004

4. An FPGA approach for high-performance multi-match priority encoder

5. Power, delay and area optimized 8-bit CMOS priority encoder for embedded applications;mohanraj;In Proceedings of the International Conference on Embedded Systems Cyber-physical Systems and Applications (ESCS) (p 1) The Steering Committee of The World Congress in Computer Science Computer Engineering and Applied Computing (WorldComp),2012

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