Architectural analysis of 1-D to 2-D array conversion of priority encoder
Author:
Publisher
Springer Science and Business Media LLC
Subject
Strategy and Management,Safety, Risk, Reliability and Quality
Link
https://link.springer.com/content/pdf/10.1007/s13198-023-01977-2.pdf
Reference23 articles.
1. Balobas D, Konofaos N (2017) High-performance and energy-efficient 256-bit cmos priority encoder. In: 2017 IEEE computer society annual symposium on VLSI (ISVLSI), pp 122–127 IEEE
2. Balobas D, Konofaos N Low-power, high-performance 64-bit cmos priority encoder using static-dynamic parallel architecture. In: 2016 5th International conference on modern circuits and systems technologies (MOCAST), pp 1–4 (2016). IEEE
3. Bao Z, Guo Y, Li X, Zhang Y, Xu M, Luo X (2020) A robust image steganography based on the concatenated error correction encoder and discrete cosine transform coefficients. J Ambient Intell Human Comput 11(5):1889–1901
4. Das S, Sen R, Dutta S, Banerjee S, Thakuria B, Jangid A, Basu R (2017) Design and simulation of all optical 4 to 2 priority encoder at 40gbps using xgm in wideband travelling wave semiconductor optical amplifier without additional input beam. In: 2017 8th IEEE annual information technology, electronics and mobile communication conference (IEMCON), pp 314–318. IEEE
5. Delgado-Frias JG, Nyathi J (2000) A high-performance encoder with priority lookahead. IEEE Trans Circuits Syst I Fund Theory Appl 47(9):1390–1393
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