A 40-Gb/s 211-1 PRBS With Distributed Clocking and a Trigger Countdown Output
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/8920/7524073/07410032.pdf?arnumber=7410032
Cited by 8 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. An active inductor employed CML latch for high speed integrated circuits;Analog Integrated Circuits and Signal Processing;2022-08-03
2. An Area Efficient Low-Power mmWave PRBS Generator in FDSOI;2022 IEEE/MTT-S International Microwave Symposium - IMS 2022;2022-06-19
3. Design of a PRBS generator and a serializer using active inductor employed CML latch;2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS);2021-08-09
4. A 15-Gb/s 0.0037-mm² 0.019-pJ/Bit Full-Rate Programmable Multi-Pattern Pseudo-Random Binary Sequence Generator;IEEE Transactions on Circuits and Systems II: Express Briefs;2020-09
5. A 1-pJ/bit 80-Gb/s $2^{15}-1$ PRBS Generator With a Modified Cherry–Hooper Output Driver;IEEE Journal of Solid-State Circuits;2019-07
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