$2\times\text{VDD}$ 40-nm CMOS Output Buffer With Slew Rate Self-Adjustment Using Leakage Compensation
Author:
Funder
Ministry of Science and Technology
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/8920/7956382/07542194.pdf?arnumber=7542194
Cited by 7 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. A 3.2-GHz 0.3/0.5 V 16-nm FinFET I/O Buffer With Low-Power PVT Compensation Circuit;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19
2. 3.2 Gbps Output Driver With Dual Low Voltage Modes and Low Power PVT Compensation Circuit;2023 IEEE International Symposium on Circuits and Systems (ISCAS);2023-05-21
3. A 2xVDD digital output buffer with gate driving stability and non-overlapping signaling control for slew-rate auto-adjustment using 16-nm FinFET CMOS process;Integration;2023-05
4. A 2.5-GHz 2×VDD 16-nm FinFET Digital Output Buffer with Slew Rate and Duty Cycle Self-Adjustment;2021 IEEE Asia Pacific Conference on Circuit and Systems (APCCAS);2021-11-22
5. Tutorial: Design of High-Speed Nano-Scale CMOS Mixed-Voltage Digital I/O Buffer With High Reliability to PVTL Variations;IEEE Transactions on Circuits and Systems II: Express Briefs;2021-02
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