Dispersed Array LDPC Codes and Decoder Architecture for NAND Flash Memory

Author:

Shao Wei,Sha Jin,Zhang Chuan

Funder

National Key Research and Development Program of China

National Natural Science Foundation of China

Project on the Industry Key Technologies of Jiangsu Province

Natural Science Foundation of Jiangsu Province

State Key Laboratory of ASIC and System

PAPD

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Cited by 15 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. An efficient GC-LDPC encoder architecture for high-speed NAND flash applications;IEICE Electronics Express;2024-01-25

2. Neural network detector with sparse codes for spin transfer torque magnetic random access memory;Cogent Engineering;2023-07-03

3. Towards LDPC Read Performance of 3D Flash Memories with Layer-induced Error Characteristics;ACM Transactions on Design Automation of Electronic Systems;2023-04-18

4. A Clustering-based ML Scheme for Capacity Approaching Soft Level Sensing in 3D TLC NAND;ICASSP 2022 - 2022 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP);2022-05-23

5. A 38.64-Gb/s Large-CPM 2-KB LDPC Decoder Implementation for nand Flash Memories;IEEE Open Journal of Circuits and Systems;2022

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