An efficient GC-LDPC encoder architecture for high-speed NAND flash applications-Reference-Cited by-同舟云学术

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An efficient GC-LDPC encoder architecture for high-speed NAND flash applications

Published:2024-01-25 Issue:2 Volume:21 Page:20230477-20230477
ISSN:1349-2543
Container-title:IEICE Electronics Express
language:en
Short-container-title:IEICE Electron. Express

Author:

Bao Binhao¹,Guan Wu²,Liang Liping²,Qiu Xin¹

Affiliation:

1. Institute of Microelectronics of the Chinese Academy of Sciences

2. Beijing University of Posts and Telecommunications

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Link

https://www.jstage.jst.go.jp/article/elex/21/2/21_20.20230477/_pdf

Reference30 articles.

1. [1] Z. Huo, et al.: “Unleash scaling potential of 3D NAND with innovative xtacking® architecture,” IEEE Symp. VLSI Circuits (2022) 254 (DOI: 10.1109/VLSITechnologyandCir46769.2022.9830285).

2. [2] Q. Li, et al.: “Exploiting asymmetric errors for LDPC decoding optimization on 3D NAND Flash memory,” IEEE Trans. Comput. 69 (2020) 475 (DOI: 10.1109/TC.2019.2959318).

3. [3] L. Cui, et al.: “A low bit-width LDPC min-sum decoding scheme for NAND Flash,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst. 41 (2022) 1971 (DOI: 10.1109/TCAD.2021.3100273).

4. [4] J. Li, et al.: “Globally coupled LDPC codes,” Inf. Theory Appl. Workshop (2016) 1 (DOI: 10.1109/ITA.2016.7888167).

5. [5] Y.-C. Liao, et al.: “A (21150, 19050) GC-LDPC decoder for NAND Flash applications,” IEEE Trans. Circuits Syst. I, Reg. Papers 66 (2019) 1219 (DOI: 10.1109/TCSI.2018.2875311).

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