Flip-Flops for Accurate Multiphase Clocking: Transmission Gate Versus Current Mode Logic-Reference-Cited by-同舟云学术

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Flip-Flops for Accurate Multiphase Clocking: Transmission Gate Versus Current Mode Logic

Published:2013-07 Issue:7 Volume:60 Page:422-426
ISSN:1549-7747
Container-title:IEEE Transactions on Circuits and Systems II: Express Briefs
language:
Short-container-title:IEEE Trans. Circuits Syst. II

Author:

Dutta Ramen,Klumperink Eric,Gao Xiang,Ru Zhiyu,van der Zee Ronan,Nauta Bram

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/8920/6558851/06520869.pdf?arnumber=6520869

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2. A 158-mW 360-MHz BW 68-dB DR Continuous-Time 1-1-1 Filtering MASH ADC in 40-nm CMOS;IEEE Journal of Solid-State Circuits;2022-12

3. Review of Ultra Low Power Receiver Front-end Designs;2021 4th International Symposium on Advanced Electrical and Communication Technologies (ISAECT);2021-12-06

4. Comprehensive study of 1-Bit full adder cells: review, performance comparison and scalability analysis;SN Applied Sciences;2021-05-17

5. A 0.002‐mm 2 8‐bit 1‐MS/s low‐power time‐based DAC (T‐DAC);IET Circuits, Devices & Systems;2021-04-08

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