A fast lock digital phase-locked-loop architecture for wireless applications
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Signal Processing
Link
http://xplorestaging.ieee.org/ielx5/82/26666/01189198.pdf?arnumber=1189198
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4. Phase‐error cancellation technique for fast‐lock phase‐locked loop;IET Circuits, Devices & Systems;2016-09
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