Phase‐error cancellation technique for fast‐lock phase‐locked loop-Reference-Cited by-同舟云学术

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Phase‐error cancellation technique for fast‐lock phase‐locked loop

Published:2016-09 Issue:5 Volume:10 Page:417-422
ISSN:1751-858X
Container-title:IET Circuits, Devices & Systems
language:en
Short-container-title:IET Circuits, Devices & Systems

Author:

Ding Zhaoming¹,Liu Haiqi¹,Li Qiang¹

Affiliation:

1. Integrated Systems LabUniversity of Electronic Science and Technology of ChinaChengdu610054People's Republic of China

Funder

National Natural Science Foundation of China

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering,Control and Systems Engineering

Link

https://onlinelibrary.wiley.com/doi/pdf/10.1049/iet-cds.2015.0201

Reference25 articles.

1. A 3–10 GHz, 14 Bands CMOS Frequency Synthesizer With Spurs Reduction for MB-OFDM UWB System

2. A 0.4–6-GHz Frequency Synthesizer Using Dual-Mode VCO for Software-Defined Radio

3. A 0.5–16.3 Gb/s Fully Adaptive Flexible-Reach Transceiver for FPGA in 20 nm CMOS

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1. Novel Power-Efficient Fast-Locking Phase-Locked Loop Based on Adaptive Time-to-Digital Converter-Aided Acceleration Compensation Technology;Electronics;2024-09-10

2. Novel Phase-frequency Detector based on Quantum-dot Cellular Automata Nanotechnology;International Journal of Engineering;2020-02

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