A 0.5–16.3 Gb/s Fully Adaptive Flexible-Reach Transceiver for FPGA in 20 nm CMOS-Reference-Cited by-同舟云学术

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A 0.5–16.3 Gb/s Fully Adaptive Flexible-Reach Transceiver for FPGA in 20 nm CMOS

Published:2015-08 Issue:8 Volume:50 Page:1932-1944
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Frans Yohan,Carey Declan,Erett Marc,Amir-Aslanzadeh Hesam,Fang Wayne Y.,Turker Didem,Jose Anup P.,Bekele Adebabay,Im Jay,Upadhyaya Parag,Wu Zhaoyin Daniel,Hsieh Kenny C. H.,Savoj Jafar,Chang Ken

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/7166356/07086092.pdf?arnumber=7086092

Cited by 14 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. 2 Lanes × 2.65-6.4 Gb/s Scalable IO Transceiver with Delay Compensation Technique in 65 nm CMOS Process;JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE;2024-06-30

2. A Flexible 0.73–15.5 GHz Single LC VCO Clock Generator in 12 nm CMOS;IEEE Transactions on Circuits and Systems II: Express Briefs;2022-11

3. An 11.05 mW/Gbps Quad-Channel 1.25-10.3125 Gbps Serial Transceiver With a 2-Tap Adaptive DFE and a 3-Tap Transmit FFE in 40 nm CMOS;IEEE Access;2021

4. Design of a Wideband dB-Linear Variable Gain Amplifier With Continuous Gain Adjusting in 90-nm CMOS Technology;IEEE Access;2021

5. Supply-Scalable High-Speed I/O Interfaces;Electronics;2020-08-15

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