2 Lanes × 2.65-6.4 Gb/s Scalable IO Transceiver with Delay Compensation Technique in 65 nm CMOS Process
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Published:2024-06-30
Issue:3
Volume:24
Page:184-190
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ISSN:2233-4866
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Container-title:JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
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language:en
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Short-container-title:JSTS
Author:
Chung Goohyung,Cho Kyoungub,Oh Taehyoun
Publisher
The Institute of Electronics Engineers of Korea