A DPLL-Based Recovery System for Nakagami-m Fading Channel

Author:

Purkayastha Basab Bijoy,Sarma Kandarpa Kumar

Publisher

Springer India

Reference13 articles.

1. Fahim AM, Elmasry MI (2003) A fast lock digital phase-locked-loop architecture for wireless applications. IEEE Trans Circuits Syst-II: Analog Digit Signal Process 50(2):63–72

2. Saber M, Jitsumatsu Y, Khan MTA (2010) Design and implementation of low power digital phase-locked loop. In: Proceedings of the ISITA2010, Taichun, Taiwan, pp 928–933

3. Stefan M, Christian V (2008) Improved lock-time in all-digital phase-locked loops due to binary search acquisition. In: Proceedings of the 15th IEEE international conference on electronics, circuits and systems, ICECS 2008, pp 384–387

4. Staszewski RB, Balsara PT (2005) Phase-domain all-digital phase-locked loop. IEEE Trans Circuits Syst II: Express Br 52(3):159–163

5. Purkayastha BB, Sarma KK (2012) Digital phase locked loop based system for Nakagami-m fading channel model. Int J Comput Appl 42(9):2370–2379

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