FPGA Qualification and Failure Rate Estimation Methodology for LHC Environments Using Benchmarks Test Circuits
Author:
Affiliation:
1. European Organization for Nuclear Research (CERN), Geneva, Switzerland
2. Dipartimento di Automatica e Informatica, Politecnico di Torino, Turin, Italy
Funder
French National Program “Programme d’Investissements d’Avenir, IRT Nanoelec”
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Nuclear Energy and Engineering,Nuclear and High Energy Physics
Link
http://xplorestaging.ieee.org/ielx7/23/9830888/09740673.pdf?arnumber=9740673
Reference23 articles.
1. Using Benchmarks for Radiation Testing of Microprocessors and FPGAs
2. Dynamic SEU Sensitivity of Designs on Two 28-nm SRAM-Based FPGA Architectures
3. LHC and HL-LHC: Present and Future Radiation Environment in the High-Luminosity Collision Points and RHA Implications
4. Thermal neutron soft error rate for SRAMs in the 90 nm–45nm technology range;wen;Proc IEEE Int Rel Phys Symp,2010
5. Thermal Neutron-Induced SEUs in the LHC Accelerator Environment
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