A 16-Gb/s backplane transceiver with 12-tap current integrating DFE and dynamic adaptation of voltage offset and timing drifts in 45-nm SOI CMOS technology-Reference-Cited by-同舟云学术

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A 16-Gb/s backplane transceiver with 12-tap current integrating DFE and dynamic adaptation of voltage offset and timing drifts in 45-nm SOI CMOS technology

Published:2011-09 Issue: Volume: Page:
ISSN:
Container-title:2011 IEEE Custom Integrated Circuits Conference (CICC)
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Author:

Gangasani Gautam R.,Hsu Chun-Ming,Bulzacchelli John F.,Rylov Sergey,Beukema Troy,Freitas David,Kelly William,Shannon Michael,Qi Jieming,Xu Hui H.,Natonio Joseph,Rasmus Todd,Guo Jong-Ru,Wielgos Michael,Garlett Jon,Sorna Michael A.,Meghelli Mounir

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/6045019/6055276/06055366.pdf?arnumber=6055366

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Clock Recovery Circuit Using a Transmission Line as a Delay Element from a 100Gb/s bit stream;2022 20th IEEE Interregional NEWCAS Conference (NEWCAS);2022-06-19

2. A digital phase‐based on‐fly offset compensation method for decision feedback equalisers;IET Circuits, Devices & Systems;2021-03-21

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