A digital phase‐based on‐fly offset compensation method for decision feedback equalisers
Author:
Affiliation:
1. School of Electrical Engineering Universidad Industrial de Santander Bucaramanga Colombia
Publisher
Institution of Engineering and Technology (IET)
Subject
Electrical and Electronic Engineering,Control and Systems Engineering
Link
https://onlinelibrary.wiley.com/doi/pdf/10.1049/cds2.12027
Reference22 articles.
1. Norimatsu T. et al.:A 25Gb/s multistandard serial link transceiver for 50db‐loss copper cable in 28nm cmos.In:International Solid State Circuit Conference San Francisco (2016)
2. Chan C.‐H. et al.:A reconfigurable low‐noise dynamic comparator with offset calibration in 90nm CMOS In:2011 IEEE Asian Solid state circuits Conference (A‐SSCC) 233–236. Macau (2011)
3. Garlepp B. et al.:A 1‐10 Gbps PAM2 PAM4 PAM2 partial response receiver analog front‐end with dynamic sampler swapping capability for backplane serial communications. In:Digest of Technical papers. 2005 Symposium on VLSI circuits 376–379. Kyoto (2005)
4. A tri‐modal 20‐Gbps/link differential/DDR3/GDDR5 memory interface;Kaviani K.;IEEE J. Solid State Circ.,2012
5. 8‐Gb/s source‐synchronous I/O link with adaptive receiver equalisation, offset cancelation, and clock de‐skew;Jaussi J.E.;IEEE J. Solid State Circ.,2005
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