Clock Recovery Circuit Using a Transmission Line as a Delay Element from a 100Gb/s bit stream
Author:
Affiliation:
1. KU Leuven,Department of Electrical Engineering,Belgium
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9841660/9841947/09842073.pdf?arnumber=9842073
Reference8 articles.
1. A 40-Gb/s Quarter-Rate SerDes Transmitter and Receiver Chipset in 65-nm CMOS
2. A 60-Gb/s 1.9-pJ/bit NRZ Optical Receiver With Low-Latency Digital CDR in 14-nm CMOS FinFET
3. A 16-Gb/s backplane transceiver with 12-tap current integrating DFE and dynamic adaptation of voltage offset and timing drifts in 45-nm SOI CMOS technology
4. Clock recovery from random binary signals
5. Low-Power Techniques for CMOS Wireline Receivers;manian;PhD thesis,2016
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