From Correctable Memory Errors to Uncorrectable Memory Errors: What Error Bits Tell

Author:

Li Cong1,Zhang Yu2,Wang Jialei1,Chen Hang1,Liu Xian2,Huang Tai1,Peng Liang2,Zhou Shen1,Wang Lixin2,Ge Shijian3

Affiliation:

1. Intel Corporation,Shanghai,China

2. ByteDance,Beijing,China

3. ByteDance,Shanghai,China

Publisher

IEEE

Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Unveiling DRAM Failures Across Different CPU Architectures in Large-Scale Datacenters;2024 IEEE 44th International Conference on Distributed Computing Systems (ICDCS);2024-07-23

2. Investigating Memory Failure Prediction Across CPU Architectures;2024 54th Annual IEEE/IFIP International Conference on Dependable Systems and Networks - Supplemental Volume (DSN-S);2024-06-24

3. Exploring Error Bits for Memory Failure Prediction: An In-Depth Correlative Study;2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD);2023-10-28

4. Predicting Future-System Reliability with a Component-Level DRAM Fault Model;56th Annual IEEE/ACM International Symposium on Microarchitecture;2023-10-28

5. HiMFP: Hierarchical Intelligent Memory Failure Prediction for Cloud Service Reliability;2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN);2023-06

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