Investigating Memory Failure Prediction Across CPU Architectures-Reference-Cited by-同舟云学术

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Investigating Memory Failure Prediction Across CPU Architectures

Published:2024-06-24 Issue: Volume:34 Page:88-95
ISSN:
Container-title:2024 54th Annual IEEE/IFIP International Conference on Dependable Systems and Networks - Supplemental Volume (DSN-S)
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Author:

Yu Qiao¹,Zhang Wengui²,Zhou Min²,Yu Jialiang²,Sheng Zhenli²,Bogatinovski Jasmin³,Cardoso Jorge¹,Kao Odej³

Affiliation:

1. Huawei Munich Research Center,Germany

2. Huawei Technologies Co., Ltd,China

3. Technical University of Berlin,Germany

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx8/10647056/10647057/10647082.pdf?arnumber=10647082

Reference41 articles.

1. What Can We Learn from Four Years of Data Center Hardware Failures?

2. An Optical Transceiver Reliability Study based on SFP Monitoring and OS-level Metric Data

3. A Class of Optimal Minimum Odd-weight-column SEC-DED Codes

4. A white paper on the benefits of chipkill correct ecc for pcserver main memory;Dell;Computer Science,1997

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