Efficient Implementation of Many-Ported Memories by Using Standard-Cell Memory Approach-Reference-Cited by-同舟云学术

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Efficient Implementation of Many-Ported Memories by Using Standard-Cell Memory Approach

Published:2023 Issue: Volume:11 Page:94885-94897
ISSN:2169-3536
Container-title:IEEE Access
language:
Short-container-title:IEEE Access

Author:

Marinberg Hanan¹,Garzón Esteban²^ORCID,Noy Tzachi¹^ORCID,Lanuzza Marco²^ORCID,Teman Adam¹^ORCID

Affiliation:

1. Emerging Nanoscaled Integrated Circuits and Systems (EnICS) Laboratories, Faculty of Engineering, Bar-Ilan University, Ramat Gan, Israel

2. Department of Computer Engineering, Modeling, Electronics and Systems, University of Calabria, Rende, Italy

Funder

Ministero dell'Universit? e della Ricerca

Magneton Program of Israel Innovation Authority

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

General Engineering,General Materials Science,General Computer Science,Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/6287639/10005208/10235320.pdf?arnumber=10235320

Reference37 articles.

1. Controlled placement of standard cell memory arrays for high density and low power in 28nm FD-SOI

2. A compact low-power 4-port register file with grounded write bitlines and single-ended read operations

3. Synthesizable Memory Arrays Based on Logic Gates for Subthreshold Operation in IoT

4. Chipyard: Integrated Design, Simulation, and Implementation Framework for Custom SoCs

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1. A 4T GC-eDRAM Bitcell with Differential Readout Mechanism For High Performance Applications;2024 19th Conference on Ph.D Research in Microelectronics and Electronics (PRIME);2024-06-09

2. Selfie5: An Autonomous, Self-Contained Verification Approach for High-Throughput Random Testing of Programmable Processors;2024 Design, Automation & Test in Europe Conference & Exhibition (DATE);2024-03-25

3. Multi-Ported GC-eDRAM Bitcell with Dynamic Port Configuration and Refresh Mechanism;Journal of Low Power Electronics and Applications;2024-01-04

4. Programmable All-in-One 4×8-/2×16-/1×32-Bits Dual Mode Logic Multiplier in 16 nm FinFET With Semi-Automatic Flow;IEEE Access;2023

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