Highly Reliable Quadruple-Node Upset-Tolerant D-Latch
Author:
Affiliation:
1. Department of Electronics and Computer Technology, University of Granada, Granada, Spain
2. High Energy Accelerator Research Organization (KEK), Oho, Tsukuba, Ibaraki, Japan
3. ECsens Group, University of Granada, Granada, Spain
Funder
Spanish Government
regional government
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
General Engineering,General Materials Science,General Computer Science
Link
http://xplorestaging.ieee.org/ielx7/6287639/9668973/09737482.pdf?arnumber=9737482
Reference35 articles.
1. Low cost soft error hardened latch designs for nano-scale CMOS technology in presence of process variation
2. A power-delay-product efficient and SEU-tolerant latch design
3. Low energy single event upset/single event transient-tolerant latch for deep subMicron technologies
4. TPDICE and Sim Based 4-Node-Upset Completely Hardened Latch Design for Highly Robust Computing in Harsh Radiation
5. A Simple Circuit Approach to Reduce Delay Variations in Domino Logic Gates
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1. CQCTL: A Cost-Optimized and Quadruple-Node-Upset Completely Tolerant Latch Design for Safety-Critical Applications;2024 IEEE International Test Conference in Asia (ITC-Asia);2024-08-18
2. A highly reliable and low-overhead quadruple-node-upset tolerant latch design;Microelectronics Reliability;2024-06
3. A Quadruple-Node Upsets Hardened Latch Design Based on Cross-Coupled Elements;Journal of Electronic Testing;2024-02
4. A High-Performance Quadruple-Node-Upset-Tolerant Latch Design and an Algorithm for Tolerance Verification of Hardened Latches;Journal of Electronic Testing;2024-02
5. Hardened latch designs based on the characteristic of transistor for mitigating multiple-node-upsets in harsh radiation environments;Microelectronics Journal;2024-01
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