A power-delay-product efficient and SEU-tolerant latch design-Reference-Cited by-同舟云学术

A power-delay-product efficient and SEU-tolerant latch design

Published:2017 Issue:23 Volume:14 Page:20170972-20170972
ISSN:1349-2543
Container-title:IEICE Electronics Express
language:en
Short-container-title:IEICE Electron. Express

Author:

Liu Pei¹²,Zhao Tian¹,Liang Feng¹,Zhao Jizhong¹,Jiang Peilin¹

Affiliation:

1. School of Microelectronics, Xi’an Jiaotong University

2. China Astronautics Standards Institute (CASI)

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Link

https://www.jstage.jst.go.jp/article/elex/14/23/14_14.20170972/_pdf

Reference19 articles.

1. [1] K. Katsarou and Y. Tsiatouhas: “Soft error interception latch: Double node charge sharing SEU tolerant design,” Electron. Lett. 51 (2015) 330 (DOI: 10.1049/el.2014.4374).

2. [2] C. Zhang and Z. Wang: “A novel reliable SEU harden latch to mitigate multi-node charge collection,” ICISCE (2012) 268 (DOI: 10.1049/cp.2012.2381).

3. [3] H. Liet al.: “SEU reliability evaluation of 3D ICs,” Electron. Lett. 51 (2015) 362 (DOI: 10.1049/el.2014.3968).

4. [4] A. Golchoobiet al.: “Effect of charge, size and temperature on stability of charged colloidal nano particles,” Chin. J. Chem. Phys. 25 (2012) 617 (DOI: 10.1088/1674-0068/25/05/617-624).

5. [5] S. Mitra, et al.: “Reliable system design: Models, metrics and design techniques,” Proc. of IEEE/ACM International Conference on Computer-Aided Design (2008) xi (DOI: 10.1109/ICCAD.2008.4681534).

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