SEU reliability evaluation of 3D ICs-Reference-Cited by-同舟云学术

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SEU reliability evaluation of 3D ICs

Published:2015-02 Issue:4 Volume:51 Page:362-364
ISSN:0013-5194
Container-title:Electronics Letters
language:en
Short-container-title:Electron. lett.

Author:

Li Huiyun¹,Hu Xiaobo²,Shao Cuiping¹,Zhou Jianbin¹,Xu Guoqing¹

Affiliation:

1. Shenzhen Institutes of Advanced Technology, Chinese Academy of Sciences, The Chinese University of Hong KongShenzhenPeople's Republic of China

2. State Grid NARI Group Corporation, Beijing NARI Smartchip Microelectronics Technology Company LimitedBeijingPeople's Republic of China

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering

Link

https://onlinelibrary.wiley.com/doi/pdf/10.1049/el.2014.3968

Reference6 articles.

1. Impact of mechanical stress on the full chip timing for TSV‐based 3D ICs;Athikulwongse K.;IEEE Trans. Comput.‐Aided Des. Integr. Circuits Syst.,2013

2. The Sorcerer's Apprentice Guide to Fault Attacks

3. The National Institute of Standards and Technology (NIST): ‘Security Requirements for Cryptographic Modules’ FIPS PUB140‐3 Draft 2009

4. On the mobility versus drain current relation for a nanoscale MOSFET

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Shallow trench isolation structure design for through‐silicon vias stress reduction;International Journal of Numerical Modelling: Electronic Networks, Devices and Fields;2022-01-23

2. A power-delay-product efficient and SEU-tolerant latch design;IEICE Electronics Express;2017

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