Soft error interception latch: double node charge sharing SEU tolerant design
Author:
Affiliation:
1. Department of Computer Science and EngineeringUniversity of Ioannina45110IoanninaGreece
Publisher
Institution of Engineering and Technology (IET)
Subject
Electrical and Electronic Engineering
Link
https://onlinelibrary.wiley.com/doi/pdf/10.1049/el.2014.4374
Reference7 articles.
1. Upset hardened memory design for submicron CMOS technology
2. Physics of multiple‐node charge collection and impacts on single‐event characterization and soft error prediction;Black J.;IEEE Trans. Nucl. Sci.,2013
3. Delay and Energy Analysis of SEU and SET-Tolerant Pipeline Latches and Flip-Flops
4. Low energy single event upset / single event transient‐ttolerant latch for seep submicron technologies;Fazeli M.;IET Comput. Digit. Tech.,2009
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