Author:
Sabeetha S.,Ajayan J.,Shriram S.,Vivek K.,Rajesh V.
Cited by
10 articles.
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1. Design and Comparison of Low Power Consumption Binary and Quaternary Multipliers;National Academy Science Letters;2023-11-22
2. Design and Analysis of Low Power MAC for DSP Processor;2023 International Conference on Artificial Intelligence and Applications (ICAIA) Alliance Technology Conference (ATCON-1);2023-04-21
3. Vedic Multiplier and Wallace Tree Adders Based Optimised Processing Element Unit for CNN on FPGA;2022 IEEE International Power and Renewable Energy Conference (IPRECON);2022-12-16
4. Design of Low Power 4-Bit Baugh-Wooley Multiplier using 1-Bit Mirror and Approximate Full Adders;2022 2nd Asian Conference on Innovation in Technology (ASIANCON);2022-08-26
5. Design and Development of Reliable Low Power High Speed 4-Bit Array Multiplier using High Performance 1-Bit Full Adders;2022 IEEE International Conference on Nanoelectronics, Nanophotonics, Nanomaterials, Nanobioscience & Nanotechnology (5NANO);2022-04-28