Vedic Multiplier and Wallace Tree Adders Based Optimised Processing Element Unit for CNN on FPGA
Author:
Affiliation:
1. RIT Kottayam,Dept. of ECE,Kottayam,India
2. RIT Kottayam,Dept. of ECE,Kottayam,Kerala,India
3. SENSE, VIT University,Vellore,Tamil Nadu,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10059458/10059467/10059532.pdf?arnumber=10059532
Reference15 articles.
1. Design Optimization of Vedic Multiplier using Reversible Logic;das;the Proceedings of International Journal of Engineering Research & Technology (IJERT),2014
2. Vedic Mathematics Sutras -A Review;shembalkar;International Conference on Recent Trends in Engineering Science and Technology (ICRTEST 2017),0
3. Ultra Low-Voltage Low-Power CMOS 4-2 and 5-2 Compressors for Fast Arithmetic Circuits
4. A High Speed 16*16 Multiplier Based On Urdhva Tiryakbhyam Sutra;raju;International Journal of Science Engineering and Advance Technology IJSEAT,2013
5. A study of performance comparison of digital multipliers using 22nm strained silicon technology
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