Memory Window in Ferroelectric Field-Effect Transistors: Analytical Approach

Author:

Toprasertpong Kasidit1ORCID,Takenaka Mitsuru1ORCID,Takagi Shinichi1ORCID

Affiliation:

1. Department of Electrical Engineering and Information Systems, The University of Tokyo, Tokyo, Japan

Funder

Japan Society for the Promotion of Science (JSPS) through JSPS KAKENHI, Japan

Japan Science and Technology Agency (JST) Core Research for Evolutional Science and Technology (CREST), Japan

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Reference23 articles.

1. High endurance strategies for hafnium oxide based ferroelectric field effect transistor

2. Critical Role of Interlayer in Hf0.5Zr0.5O2 Ferroelectric FET Nonvolatile Memory Performance

3. Re-examination of Vth window and reliability in HfO? FeFET based on the direct extraction of spontaneous polarization and trap charge during memory operation;ichihara;IEEE Symp VLSI Tech,2020

4. Compact modeling of multidomain ferroelectric FETs: Charge trapping, channel percolation, and nucleation-growth domain dynamics;xiang;IEEE Trans Electron Device,2018

5. Device modeling of ferroelectric memory field-effect transistor (FeMFET)

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