Comprehensive TCAD-Based Validation of Interface Trap-Assisted Ferroelectric Polarization in Ferroelectric-Gate Field-Effect Transistor Memory-Reference-Cited by-同舟云学术

Comprehensive TCAD-Based Validation of Interface Trap-Assisted Ferroelectric Polarization in Ferroelectric-Gate Field-Effect Transistor Memory

Published:2022-03 Issue:3 Volume:69 Page:1048-1053
ISSN:0018-9383
Container-title:IEEE Transactions on Electron Devices
language:
Short-container-title:IEEE Trans. Electron Devices

Author:

Lee Kitae¹^ORCID,Kim Sihyun¹^ORCID,Kim Munhyeon¹^ORCID,Lee Jong-Ho¹^ORCID,Kwon Daewoong²^ORCID,Park Byung-Gook¹^ORCID

Affiliation:

1. Department of Electrical and Computer Engineering and the Inter-University Semiconductor Research Center, Seoul National University, Seoul, South Korea

2. Department of Electrical Engineering, Inha University, Incheon, South Korea

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx7/16/9722602/09701595.pdf?arnumber=9701595

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4. Re-Examination of Vth Window and Reliability in HfO2 FeFET Based on the Direct Extraction of Spontaneous Polarization and Trap Charge during Memory Operation

5. Impact of Charges at Ferroelectric/Interlayer Interface on Depolarization Field of Ferroelectric FET With Metal/Ferroelectric/Interlayer/Si Gate-Stack

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