Proposal and Investigation of Area Scaled Nanosheet Tunnel FET: A Physical Insight
Author:
Affiliation:
1. Department of Electronics Engineering, VLSI Design Group, Sardar Vallabhbhai National Institute of Technology, Surat, Gujarat, India
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Link
http://xplorestaging.ieee.org/ielx7/16/9839401/09810871.pdf?arnumber=9810871
Reference30 articles.
1. Lateral InAs/Si p-Type Tunnel FETs Integrated on Si—Part 2: Simulation Study of the Impact of Interface Traps
2. ${\rm Si}_{\rm x}{\rm Ge}_{1\hbox{-}{\rm x}}$ Epitaxial Tunnel Layer Structure for P-Channel Tunnel FET Improvement
3. Drain Current Saturation in Line Tunneling-Based TFETs: An Analog Design Perspective
4. Layout Design Correlated With Self-Heating Effect in Stacked Nanosheet Transistors
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