Influences of Source/Drain Extension Region on Thermal Behavior of Stacked Nanosheet FET-Reference-Cited by-同舟云学术

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Influences of Source/Drain Extension Region on Thermal Behavior of Stacked Nanosheet FET

Published:2024-03 Issue:3 Volume:71 Page:2171-2176
ISSN:0018-9383
Container-title:IEEE Transactions on Electron Devices
language:
Short-container-title:IEEE Trans. Electron Devices

Author:

Srivastava Shobhit¹^ORCID,Panwar Sourabh¹^ORCID,Shashidhara M.¹^ORCID,Chandra Lomash²^ORCID,Mishra Neeraj³,Acharya Abhishek¹^ORCID

Affiliation:

1. Department of Electronics Engineering, VLSI Design Group, Sardar Vallabhbhai National Institute of Technology, Surat, Gujarat, India

2. Department of Electronics and Communication Engineering, IIT Roorkee, Roorkee, Uttarakhand, India

3. IDLab, Ghent University, Ghent, Belgium

Funder

Science and Engineering Research Board, Department of Science and Technology, Government of India

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Link

http://xplorestaging.ieee.org/ielx7/16/10457976/10403811.pdf?arnumber=10403811

Reference21 articles.

1. Impact of aggressive fin width scaling on FinFET device characteristics

2. Challenges and Limitations of CMOS Scaling for FinFET and Beyond Architectures

3. Proposal and Investigation of Area Scaled Nanosheet Tunnel FET: A Physical Insight

4. Device Exploration of NanoSheet Transistors for Sub-7-nm Technology Node

5. Electro-Thermal Performance Boosting in Stacked Si Gate-all-Around Nanosheet FET With Engineered Source/Drain Contacts

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Study on trap sensitivity for single material gate and double material gate nano-ribbon FETs;Physica Scripta;2024-06-20

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