Two Double-Node-Upset-Hardened Flip-Flop Designs for High-Performance Applications-Reference-Cited by-同舟云学术

Two Double-Node-Upset-Hardened Flip-Flop Designs for High-Performance Applications

Published:2023-10 Issue:4 Volume:11 Page:1070-1081
ISSN:2168-6750
Container-title:IEEE Transactions on Emerging Topics in Computing
language:
Short-container-title:IEEE Trans. Emerg. Topics Comput.

Author:

Yan Aibin¹^ORCID,Cao Aoran²^ORCID,Huang Zhengfeng¹^ORCID,Cui Jie²^ORCID,Ni Tianming³^ORCID,Girard Patrick⁴^ORCID,Wen Xiaoqing⁵^ORCID,Zhang Jiliang⁶^ORCID

Affiliation:

1. School of Microelectronics, Hefei University of Technology, Hefei, Anhui, China

2. School of Computer Science and Technology, Anhui University, Hefei, Anhui, China

3. School of Integrated Circuits, Anhui Polytechnic University, Wuhu, Anhui, China

4. LIRMM, University of Montpellier/CNRS, Montpellier, France

5. Graduate School of Computer Science and Systems Engineering, Kyushu Institute of Technology, Fukuoka, Japan

6. College of Semiconductors (College of Integrated Circuits), Hunan University, Changsha, Hunan, China

Funder

National Natural Science Foundation of China

Open Project of the State Key Laboratory of Computing Institute of the Chinese Academy of Sciences

NSFC-JSPS Exchange Program

Outstanding Young Talent Support Program Key Project of Anhui Provincial Universities

Distinguished Young Scholar Fund of Anhui Province

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Computer Science Applications,Human-Computer Interaction,Information Systems,Computer Science (miscellaneous)

Link

http://xplorestaging.ieee.org/ielx7/6245516/10349221/10262220.pdf?arnumber=10262220

Reference39 articles.

1. Soft-Error-Aware Read-Stability-Enhanced Low-Power 12T SRAM With Multi-Node Upset Recoverability for Aerospace Applications

2. DAD-FF: Hardening Designs by Delay-Adjustable D-Flip-Flop for Soft-Error-Rate Reduction

3. A Methodology for Characterization of SET Propagation in SRAM-Based FPGAs

4. A Highly Robust and Low-Power Real-Time Double Node Upset Self-Healing Latch for Radiation-Prone Applications

5. Design and Evaluation of Low-Complexity Radiation Hardened CMOS Latch for Double-Node Upset Tolerance

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