A single-V/sub t/ low-leakage gated-ground cache for deep submicron-Reference-Cited by-同舟云学术

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A single-V/sub t/ low-leakage gated-ground cache for deep submicron

Published:2003-02 Issue:2 Volume:38 Page:319-328
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:en
Short-container-title:IEEE J. Solid-State Circuits

Author:

Agarwal A.,Hai Li ,Roy K.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx5/4/26391/01175513.pdf?arnumber=1175513

Cited by 73 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Comparison of Techniques for Reducing Leakage Current in SRAM: A Study of Gated V_DD, MTCMOS, and Clamping Diode Techniques;2024 International Conference on Recent Advances in Electrical, Electronics, Ubiquitous Communication, and Computational Intelligence (RAEEUCCI);2024-04-17

2. At the Locus of Performance: Quantifying the Effects of Copious 3D-Stacked Cache on HPC Workloads;ACM Transactions on Architecture and Code Optimization;2023-12-14

3. Analysis of back-gate bias impact on 22 nm FDSOI SRAM cell;Solid-State Electronics;2022-10

4. CORIDOR: Using CO herence and Tempo R al Local I ty to Mitigate Read D isurbance Err OR in STT-RAM Caches;ACM Transactions on Embedded Computing Systems;2022-01-14

5. Ultralow-Voltage Retention SRAM With a Power Gating Cell Architecture Using Header and Footer Power-Switches;IEEE Open Journal of Circuits and Systems;2021

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