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Ultralow-Voltage Retention SRAM With a Power Gating Cell Architecture Using Header and Footer Power-Switches

  • Published:2021 Issue: Volume:2 Page:520-533
  • ISSN:2644-1225
  • Container-title:IEEE Open Journal of Circuits and Systems
  • language:
  • Short-container-title:IEEE Open J. Circuits Syst.

Author:

Yoshida HayatoORCID,Shiotsu YusakuORCID,Kitagata Daiki,Yamamoto Shuu'ichirou,Sugahara Satoshi

Funder

VLSI Design and Education Center (VDEC), The University of Tokyo, in collaboration with NIHON SYNOPSYS G.K

Renesas Electronics Corp

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

General Medicine

Cited by 4 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Dual Power Gating 8-Transistor SRAM Design For Low Power Applications;2023 International Conference on System Science and Engineering (ICSSE);2023-07-27

2. Dalorex: A Data-Local Program Execution and Architecture for Memory-bound Applications;2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA);2023-02

3. Binarized Neural Network Accelerator Macro Using Ultralow-Voltage Retention SRAM for Energy Minimum-Point Operation;IEEE Journal on Exploratory Solid-State Computational Devices and Circuits;2022-12

4. 40nm Ultra-low Leakage SRAM with Embedded Sub-threshold Analog Closed Loop System for Efficient Source Biasing of the Memory Array in Retention Mode;2022 35th International Conference on VLSI Design and 2022 21st International Conference on Embedded Systems (VLSID);2022-02
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