Affiliation:
1. Laboratory for Future Interdisciplinary Research of Science and Technology, Tokyo Institute of Technology, Yokohama, Japan
Funder
Japan Society for the Promotion of Science
VLSI Design and Education Center (VDEC), The University of Tokyo, in collaboration with Nihon Synopsys G.K., Cadence Design Systems, Mentor Graphics, and Renesas Electronics Corporation
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Hardware and Architecture,Electronic, Optical and Magnetic Materials
Reference22 articles.
1. XNOR-Net: ImageNet classification using binary convolutional neural networks;rastegari;arXiv 1603 05279,2016
2. The trend of functional memory development;tamaru;IEICE Trans Electron,1993
3. A 280 mV-to-1.2 V wide-operating-range IA-32 processor in 32 nm CMOS;jain;IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers,2012
4. Enabling AI at the edge with XNOR-networks
5. Ultralow-Voltage Retention SRAM With a Power Gating Cell Architecture Using Header and Footer Power-Switches