The 65-nm 16-MB Shared On-Die L3 Cache for the Dual-Core Intel Xeon Processor 7100 Series-Reference-Cited by-同舟云学术

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The 65-nm 16-MB Shared On-Die L3 Cache for the Dual-Core Intel Xeon Processor 7100 Series

Published:2007-04 Issue:4 Volume:42 Page:846-852
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Chang Jonathan,Huang Ming,Shoemaker Jonathan,Benoit John,Chen Szu-Liang,Chen Wei,Chiu Siufu,Ganesan Raghuraman,Leong Gloria,Lukka Venkata,Rusu Stefan,Srivastava Durgesh

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx5/4/4140573/04140574.pdf?arnumber=4140574

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5. INTERPLAY: An Intelligent Model for Predicting Performance Degradation due to Multi-cache Way-disabling;2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT);2022-10-19

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