Automated Design of Chiplets

Author:

Sangiovanni-Vincentelli Alberto1ORCID,Liang Zheng1ORCID,Zhou Zhe2ORCID,Zhang Jiaxi2ORCID

Affiliation:

1. University of California, Berkeley, Berkeley, CA, USA

2. Peking University, Beijing, China

Funder

Cadence Design Systems

National Research Foundation Singapore

Publisher

ACM

Reference48 articles.

1. Paul Alcorn. 2023. AMD Instinct MI300 Data Center APU Pictured Up Close: 13 Chiplets 146 Billion Transistors. https://www.tomshardware.com/news/amd-instinct-mi300-data-center-apu-pictured-up-close-15-chiplets-146-billion-transistors Retrieved January 05 2023 from Paul Alcorn. 2023. AMD Instinct MI300 Data Center APU Pictured Up Close: 13 Chiplets 146 Billion Transistors. https://www.tomshardware.com/news/amd-instinct-mi300-data-center-apu-pictured-up-close-15-chiplets-146-billion-transistors Retrieved January 05 2023 from

2. The IBM RISC System/6000 processor: Hardware overview

3. Networks on chips: a new SoC paradigm

4. Idan Burstein . 2021 . Nvidia Data Center Processing Unit (DPU) Architecture. In 2021 IEEE Hot Chips 33 Symposium (HCS). 1--20 . Idan Burstein. 2021. Nvidia Data Center Processing Unit (DPU) Architecture. In 2021 IEEE Hot Chips 33 Symposium (HCS). 1--20.

5. Bill Chang , Rajiv Kurian , Doug Williams , and Eric Quinnell . 2022 . DOJO: Super-Compute System Scaling for ML Training. In 2022 IEEE Hot Chips 34 Symposium (HCS). 1--45 . Bill Chang, Rajiv Kurian, Doug Williams, and Eric Quinnell. 2022. DOJO: Super-Compute System Scaling for ML Training. In 2022 IEEE Hot Chips 34 Symposium (HCS). 1--45.

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