A High Linearity, Fast-Locking Pulsewidth Control Loop With Digitally Programmable Duty Cycle Correction for Wide Range Operation-Reference-Cited by-同舟云学术

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A High Linearity, Fast-Locking Pulsewidth Control Loop With Digitally Programmable Duty Cycle Correction for Wide Range Operation

Published:2008 Issue:2 Volume:43 Page:399-413
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Cheng Kuo-Hsing,Su Chia-Wei,Chang Kai-Fei

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx5/4/4444554/04444556.pdf?arnumber=4444556

Cited by 35 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Adaptive Clock Gating for Improving Wear out induced Duty Cycle Shift in the Clock Network;2024 IEEE International Reliability Physics Symposium (IRPS);2024-04-14

2. A 30 kHz - 3 GHz Clock Duty-Cycle Corrector Circuit for CMOS Integrated Digital Electronic Systems;2023 30th International Conference on Mixed Design of Integrated Circuits and System (MIXDES);2023-06-29

3. A duty cycle corrector with dual loop low pass filter for low jitter and fast correction time;AEU - International Journal of Electronics and Communications;2023-04

4. Design and Analysis of Asynchronous Sampling Duty Cycle Corrector;Electronics;2021-10-24

5. A 2.1 GHz, 210 μW, —189 dBc/Hz DCO with Ultra Low Power DCC Scheme;Electronics;2021-03-29

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